The density of integrated circuits that may be deposited on a substrate is growing much more rapidly than the density of pads used to connect the integrated circuit to circuits outside the integrated circuit's package. Thus, bottlenecks occur in signal transfer to and from an integrated circuit. These bottlenecks occur in highly-configurable system-on-a-chip (SOC) integrated circuits rendering the SOC in/out (I/O) limited. SOC's contain numerous peripheral circuits, many of which are not used in all applications of the SOC. If physical I/O requirements of all SOC peripherals are supported, either the SOC is large in size or is I/O limited.
In addition, market demand is driving a desire for increased integrated circuit versatility. For example, it is desirable to produce an audio processing chip that may connect to other circuits by many different industry standard interfaces without having a multitude of unused pads and unused through-package conductors. It is inefficient to manufacture a chip having these unused conductors.
Also, integrated circuits are currently designed so a circuit board designer is constrained by a chip manufacturer's pinout of the integrated circuit package. It is desirable to increase flexibility of an integrated circuit's pinout so circuit board designers have greater flexibility in board design. Pinout flexibility may be increased by providing a way to use a minimum number of integrated circuit leads with a maximum number of circuits on a substrate.
Another problem with current integrated circuit manufacturing techniques is that integrated circuits with failed sections of circuitry are often discarded. It is desirable to salvage as many of these chips as possible by using them in some productive manner. Salvaging would minimize waste and thus increase fabrication facility efficiency.
Finally, integrated circuit testing often requires looping of signals from an integrated circuit under test back to the integrated circuit under test. Loopback currently takes place externally to a chip and thus requires external circuitry. It is desirable to reduce circuitry external to a chip to reduce testing costs and therefore reduce fabrication facility costs while increasing fabrication facility efficiency.
Accordingly, what is needed is an apparatus and method that overcomes the shortcomings noted above.